FIG. 1 of the accompanying drawings is a block schematic diagram of a simplified radio receiver and illustrates a classical radio frequency (RF) AGC system. An antenna 10 is coupled to a gain controlled RF amplifier 12. An output of the RF amplifier 12 is coupled to a simplified frequency down-conversion stage 14 in which a received RF signal is frequency down-converted to base band and applied to a demodulator 16. The architecture of the frequency down-conversion stage 14 can be of any suitable design known in the art and for the purpose of illustration comprises a superheterodyne stage comprising a mixer 18 having inputs for the output of the RF amplifier 12 and a local oscillator 20, respectively. A bandpass filter 22 is coupled to an output of the mixer 18 to select the desired signal from the products of mixing. A baseband or audio frequency gain controlled amplifier 24 has an input coupled to an output of the bandpass filter 22 and an output coupled to an input of the demodulator 16.
Broadly stated the purpose of AGC is to adjust automatically the gain of the receiver such as to enable the receiver to deliver an adequate level of signal to the input of the demodulator 16. As an example if it assumed that the demodulator is an analog-to-digital converter (ADC) with a 1 Vpp range, then, the adequate level delivered by the receiver output should be 1 Vpp.
In the circuit illustrated in FIG. 1, AGC is applied to the RF amplifier 12 and to the baseband amplifier 24. The signal received at the antenna 10 is a broadband signal shown by the inset drawing, the broadband signal includes the desired signal fW and unwanted signals in adjacent bands. The total power received from the antenna at an input of the RF amplifier 12 is Ptot. The power of the amplified broadband signal at the output of the RF amplifier 12 is Pout and this power is detected at the output of the amplifier 12 using a power detector 26. The power detector 26 produces an output Pdet which is applied to one input of a comparator 28. A threshold stage 30 is connected to a second input of the comparator 28 and provides a threshold value against which Pdet is compared. The threshold value is selected to maximise the gain of the RF amplifier 12. An output of the comparator 28 is coupled to an integrator 32 which has an output coupled to a control input 13 of the RF amplifier 12. In operation if Pdet exceeds the threshold value then the AGC circuit reduces the gain of the RF amplifier 12 and conversely if Pdet is less than the threshold value the AGC circuit increases the gain of the RF amplifier 12. This process continues with the objective of adjusting the gain until Pdet equals the threshold. In practice Pout is regulated in order to avoid overloading the stages following the RF amplifier 12, in this illustrated case, the frequency down-conversion stages. The base band amplifier 24 receives a narrowband signal, shown inset, comprising the desired signal fW and, possibly, residues fR from the adjacent channels depending on the quality of filtering by the bandpass filter 22 and provides an amplified constant level output signal fWCL to the demodulator 16. In order to control the gain of the base band amplifier an output derived from the demodulator 16 is applied to a control input 25 of the base band amplifier 24 in order to keep its output constant.
US Patent Application Publication US 2003/0143967 A1 discloses applying AGC to an analog cellular telephone receiver having a zero-IF or low-IF architecture. In the interests of brevity, the architecture of the zero-IF converter, filters and ADCs will not be described as these are well known in the art. Compared to the architecture shown in FIG. 1, the gain controlled RF amplifier is a LNA and the baseband amplifier comprises a digital variable gain amplifier (VGA) whose outputs are coupled to a digital FM demodulator. The voltages at the outputs of the digital VGA are also coupled to an accumulator. An output of the accumulator is coupled to a controller for providing gain control signals to be applied to the LNA and the digital VGA in order to maintain the average power gain to be equal to a constant set point supplied to the controller. In the LNA the gain is adjusted in gain steps and this has the effect of introducing unwanted phase shifts into the RF signals from the LNA. In order to eliminate the unwanted phase shifts, a phase shifter controlled by the controller is connected into the quadrature related signal paths to the inputs of the digital VGA. The controller is synchronised to apply a respective phase correction just as the gain adjusted signal reaches the phase shifter, this is done by applying to a phase correction signal a group delay corresponding to the signal propagation delay between the LNA and the phase shifter.
A drawback to the known AGC circuits is that the gain is set as high as possible in the first stages in order to achieve a good noise figure whilst at the same time avoiding introducing excessive non-linearities which could lead to degradation of the wanted signal as well as the unwanted signals. As a consequence these stages are designed to achieve sufficient linearity and this in turn leads to a high power consumption which is undesirable in battery powered devices. The dominant source of signal degradation is then thermal noise.